(a) Field of the Invention
The present invention relates to insulated gate type semiconductor device, and more particularly it pertains to insulated gate type semiconductor device such as insulated gate type static induction transistor which exhibits non-saturating type current vs. voltage characteristic.
(b) Description of the Prior Art
The known insulated gate type field effect transistor (hereinafter to be referred to as IG-FET) exhibits a so-called saturating type current vs. voltage characteristic whereby the drain current becomes saturated beyond a pinch-off drain voltage. In addition, the known IG-FET exhibits a large gate-source capacitance C.sub.gs, a large gate-drain capacitance C.sub.gd, and a large gate-substrate capacitance C.sub.gsub, all of which serve as factors for hampering high-speed operation. Attempts are being made to enlarge transconductance and to reduce the aforesaid respective capacitances by reducing the channel length of the transistor. However, where it is intended to obtain a saturating type current vs. voltage characteristic from a transistor having a reduced length of channel, it becomes necessary to elevate the impurity concentration of the channel region. This, in turn, usually requires that the thickness of the insulating layer provided on the channel region be made small, and accordingly the manufacture of such transistor becomes difficult. On the other hand, it has been reported that where the channel length, i.e. the distance between the source and the drain, is reduced while the impurity concentration of the channel region is maintained at a similar magnitude, a non-saturating type current vs. voltage characteristic is obtained (P. Richman: "Modulation of space-charge-limited current flow in insulated-gate field effect tetrodes", IEEE Trans. on Electron Devices, Vol. ED-16, No. 9. p.p. 759-766, Sept., 1969). Such IG-FET is called "punch-through IG-FET", and as will be noted also from the title of the paper of Richman, the current flow is identified as space-charge-limited current. Apart from this, the present inventor has proposed a static induction transistor (hereinafter to be referred to as SIT) based on the discovery that the current saturation mechanism of known FET's (including junction FET and MOS FET) is ascribed to the negative feedback action of the series resistance from the source inclusive to the pinch-off point or pinched off portion inclusive. The SIT provides a non-saturating type current vs. voltage characteristic by reducing the channel length in order to reduce the aforesaid series resistance (Japanese Patent Publication NO. 52-6076). In an SIT having a channel region of the same conductivity type as that of the source region, even in the state that a potential barrier is produced in the channel by the depletion layer extending from the gate, the height of this potential barrier can be pulled down due to a static induction effect when a drain voltage is applied, and accordingly the drain current increases. This SIT no doubt includes, as a mode of operation, the state that the depletion layer extending from the gate does not cover all the channel, so that a neutral region remains locally in the channel connecting the source and the drain regions. Thus, in a certain gate bias state, the SIT provides operation of the "potential barrier height control type", i.e. the type where the current vs. voltage characteristic follows an exponential function in a low drain current region. In another certain gate bias state, a neutral region is present in the channel so that in a low current region, the transistor exhibits substantially a current vs. voltage characteristic of the type that depends almost entirely on the resistance of the neutral (non-depleted) channel region. It should be understood also that there can be an SIT which operates only under the channel condition where a potential barrier is formed in a current channel and carriers must traverse this potential barrier in flowing from the source to the drain.
A structure of the known IG-FET of n-channel type having a reduced channel length intended to reduce the series resistance is shown in FIG. 1. In this Figure, n.sup.+ type regions 11 and 12 represent a source region and a drain region, respectively, and a p type region 14 represents a substrate. Numerals 11' and 12' represent a source electrode and a drain electrode, respectively. They are ordinarily made with a metal such as aluminum. There may be an instance wherein a low resistivity polysilicon intervenes between the semiconductor crystal and the metal. Numeral 13 represents a gate electrode which is formed on top of a thin insulating layer, and this gate electrode may be made with a metal such as Al, Mo and W, or with a low resistivity polysilicon. In the structure shown in FIG. 1, it should be understood that, if the channel length, i.e. the distance between the source region 11 and drain region 12, is reduced while maintaining the impurity concentration of the p type region 14 at a similar value, the series resistance will be reduced and at the same time therewith the influence of the drain voltage will reach directly to the source region. Thus, electrons will also be injected from the deep-located portion of the source region that is remote from the semiconductor surface, and will form part of the drain current. Those electrons flowing through a deep portion of the semiconductor body can hardly be controlled by the gate voltage. Hence the efficiency of control of the drain current by the gate voltage will not be large, and the transconductance will become small.